Reliable Minimum Energy CMOS Circuit Design

Low voltage operation can markedly reduce the energy requirements of digital circuits; however, in the face of variability it also greatly reduces the reliability and yield. In order to mitigate this effect, device dimensions can be increased and adaptive body biasing can be employed, but at the cost of potentially increasing energy per operation. This paper presents a new framework for determining the minimum energy operating point of digital CMOS circuits with precise guarantees on reliability and parametric yield.